The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...
For those not immediately familiar with RISC-V, it is a relatively new CPU architecture which takes advantage of Reduced Instruction Set Computer (RISC) principles. RISC-V is an open standard ...
SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive, Inc., the industry leader in RISC-V processors and silicon solutions, today launched the new SiFive Performance family of processors. The SiFive Performance ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback